1. Field of the Invention
The present invention generally relates to a ferroelectric memory element, and more particularly, to a non-volatile memory capable of controlling current between a source and a drain of a transistor by using a ferroelectric thin film at a gate thereof and a non-volatile memory using electric charge of a ferroelectric capacitor.
2. Description of the Related Art
Conventionally, a ferroelectric non-volatile memory FRAM (Ferroelectric Random Access Memory) which has been reduced into practice, is operated at low voltage. Further, the ferromagnetic non-volatile memory FRAM is regarded to be more excellent than conventional EEPROM (Electrically Erasable and Programmable Read Only Memory), Flash Memory or the like in view of its superior rewriting ability. However, a FRAM is provided with a structure in which a capacitor of DRAM is replaced by a ferroelectric capacitor (described in Japanese Patent Laid-Open No. 1113496/1990) and needs to rewrite at each reading of data. Either of the reading and writing operation is accompanied by polarization inversion of a ferroelectric material such that fatigue of the ferromagnetic material is significant. Further, either of the operations is accompanied by charging and discharging of the capacitor and therefore, an operational time period thereof requires about 100 nsec. Further, it is necessary to separately provide a transistor and a capacitor, which is disadvantageous in attempts to reduce the area of the device in order to provide for large capacity storage devices.
In contrast thereto, in the case of MFS-FET (Metal Ferroelectric Semiconductor Field Effect Transistor) using a ferroelectric material at a gate insulating film portion of a transistor, an interval between a source and a drain of a transistor is made ON and OFF by inducing electric charge of a channel of the transistor by polarizing the ferroelectric material and even when a cell area is proportionally reduced, a rate of changing drain current remains unchanged. This signifies that a memory cell of a ferroelectric transistor follows a scaling rule (Proceeding of Electronic, Information and Communication Society 77-9, p. 976, 1994) and there is not present a limit in view of a miniaturization principle. Further, a transistor type ferroelectric memory maintains ON and OFF of FET by polarizing a ferroelectric material and accordingly, information is not destroyed by reading operation at low voltage. A xe2x80x9cnon-destructivexe2x80x9d reading operation can be carried out.
However, in the case of the structure, when there is constructed an MFS structure formed with a ferroelectric material directly above a silicon semiconductor substrate and formed with an upper electrode thereabove, carriers on the side of the silicon semiconductor substrate are implanted into the ferroelectric material (S. Y. Wu, IEEE Trans. Electron Devices: Vol. ED-21, No. 8, pp. 499-504 (1974)), mutual diffusion is caused between the silicon semiconductor substrate and the ferroelectric material (Jpn. J. Appl. Phys., Vol. 33, pp 5172 (1994)) and accordingly, there is not achieved an FET (Field Effect Transistor) characteristic operating adequately.
Hence, there have been proposed an MFIS-FET (Metal Ferroelectric Insulator Semiconductor FET) structure interposing a buffer layer of an insulating film between a silicon semiconductor substrate and a ferroelectric material as disclosed in Japanese Patent Laid-Open No. 64206/1997, an MFMIS-FET (Metal Ferroelectrics Metal Insulator Semiconductor-FET) interposing a metal (M) layer between a ferroelectric layer having the MFIS structure and an insulating film (T. Nakamura et al. Dig. Tech. Pap. of 1995 IEEE Int. Solid State Circuits Conf. p. 68 (1995)) and so on. The invention relates to the MFIS structure of the former.
FIG. 5 shows a section of a simplified principle view of a conventional MFIS type ferroelectric memory. In FIG. 5, a main face of a semiconductor substrate is formed with a source region and a drain region and a middle portion of the main face of the semiconductor substrate is formed with a buffer layer of an insulating film. A ferromagnetic layer and a conductor layer are laminated above the buffer layer of the insulating film.
FIG. 6 represents a portion of the MFIS structure of FIG. 5 by an equivalent circuit. FET using a ferroelectric material at a portion of a gate insulating film of a transistor utilizes polarization generated at the ferroelectric layer and accordingly, when an electric field equal to or larger than the resistance electric field is not applied to the ferroelectric layer, the polarization cannot be caused and FET does not operate as an non-volatile memory. Further, in view of a memory holding characteristic, it is necessary to apply voltage until the polarization of the ferroelectric layer is sufficiently saturated. For that purpose, when voltage is applied between an upper electrode A and the semiconductor substrate B, it is necessary to increase voltage distributed to capacitance CF (capacitance of ferroelectric layer) and for that purpose, it is important to design the insulating film such that capacitance CI (capacitance of buffer layer of insulating film) becomes larger than the capacitance CF (capacitance of ferroelectric layer). The capacitance CI and the capacitance CF are governed by a relationship in which the capacitance CI or the capacitance CF is proportional to relative dielectric constant and area of the buffer layer of the insulating film or the ferroelectric layer applied with voltage and is inversely proportional to a thickness thereof.
Although it is conceivable to make the area of the buffer layer of the insulating film larger than the area of the ferroelectric capacitance as a method of enabling the design, in the case of the MFIS structure, the area of the ferroelectric capacitance and the area of the gate insulating film of the buffer layer are determined by an area of the conductor film above the ferroelectric layer and accordingly, the area ratio cannot be changed.
Although it is conceivable to thin the buffer layer of the insulating film and to thicken the ferroelectric layer in order to design such that a capacitance CI becomes larger than the capacitance CF as other method, there is a limit in thinning the gate insulating layer in view of withstand voltage and leakage current and when the ferroelectric layer is thickened, in order to saturate the polarization of the ferroelectric material, high polarization voltage is needed and drive voltage becomes high.
A method of increasing the capacitance CI avoiding the problems mentioned above, is a method of using a material having high relative dielectric constant at the buffer layer of the insulating film. For example, the capacitance CI 
According to a method of forming the buffer layer of the insulating film, CeO2 is directly deposited on the silicon semiconductor substrate in an oxygen atmosphere at 900xc2x0 C. by electron beam vacuum vapor deposition and the coated layer is annealed in an oxygen atmosphere (700xc2x0 C.) in order to lower the interface level, thereafter, annealed in an oxygen atmosphere in order to deposit and crystallize the ferroelectric thin film.
However, in this case, in forming the buffer layer and the ferroelectric thin film, by forming a low dielectric constant layer of SiO2 or CeOx or the like between the silicon semiconductor substrate and the buffer layer, the film thickness is increased, the capacitance C1 of the buffer layer of the insulating film is lowered and distributed voltage applied to the ferroelectric layer is reduced. As a result, there poses a problem that when the distributed voltage applied to the ferroelectric layer is low, voltage applied to the gate electrode must be increased and the MFIS type ferroelectric memory cannot be used unless drive voltage is increased.
Hence, it is an object of the invention to provide a ferroelectric memory element having high reliability and a large reading margin capable of applying sufficient distributed voltage to a ferromagnetic thin film by restraining capacitance of a buffer layer of an insulating film from lowering by restraining an interval between a silicon semiconductor substrate and a buffer layer of an insulating film from forming a low dielectric constant layer.
In order to achieve the above-described object, according to an aspect of the present invention, there is provided a ferroelectric memory element which is a ferroelectric memory element having a structure of successively laminating an insulating film and a ferroelectric film above a silicon semiconductor substrate, wherein the insulating film includes a low dielectric constant layer restraining film and a mutual diffusion preventive film.
Further, according to another aspect of the invention, the low dielectric constant layer restraining film of the ferroelectric memory element includes nitrogen in a vicinity of a surface of the silicon semiconductor substrate and the means for restraining the low dielectric constant layer is constituted by the element of nitrogen.
According to another aspect of the invention, the mutual diffusion preventive film of a ferroelectric memory element above the silicon semiconductor substrate includes nitrogen.
According to another aspect of the invention, the low dielectric constant layer restraining film provided in the insulating film is a silicon oxynitride film or a silicon nitride film. The mutual diffusion preventive film provided in the insulating film is a layer of one material or a layer laminated with two or more of materials selected from the group consisting of CeO2, Cexe2x80x94ZrO2, YSZ (yttrium oxide stabilized zirconium oxide), Y2O3, SrTiO3, ZrO2, HfO2 and (BaSr)TiO3 (BST). The ferroelectric thin film is a thin film of one material selected from the group consisting of PbTiO3, PbZrXTi1xe2x88x92XO3, PbYLa1xe2x88x92YZrXTi1xe2x88x92XO3, Bi4Ti3O12, Sr2Nb2O7, Sr2(TaXNb1xe2x88x92X)2O7 and SrBi2Ta2O9.